H@8;( ;Uedgeble,neural-compute-module-6a-ioedgeble,neural-compute-module-6arockchip,rk3588 +7Edgeble Neu6A IO Boardaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci+ 2 B0,W gt@@   cpu@100cpuarm,cortex-a55 psci+ W gt@@  cpu@200cpuarm,cortex-a55 psci+ W gt@@  cpu@300cpuarm,cortex-a55 psci+ W gt@@  cpu@400cpuarm,cortex-a76 psci+ 2 B0,W gt@@ cpu@500cpuarm,cortex-a76 psci+ W gt@@ cpu@600cpuarm,cortex-a76 psci+ 2 B0,W gt@@ cpu@700cpuarm,cortex-a76 psci+ W gt@@  idle-states pscicpu-sleeparm,idle-state->Udfxv l2-cache-l0cacheiv@ l2-cache-l1cacheiv@l2-cache-l2cacheiv@l2-cache-l3cacheiv@l2-cache-b0cacheiv@l2-cache-b1cacheiv@l2-cache-b2cacheiv@l2-cache-b3cacheiv@l3-cachecachei0v@display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32kreserved-memory+shmem@10f000arm,scmi-shmemgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf 2 B +corecoregroupstacks 0\]^ jobmmugpu*  8disabled!usb@fc000000rockchip,rk3588-dwc3snps,dwc3@+ref_clksuspend_clkbus_clk?otg G"#Lusb2-phyusb3-phy Vutmi_wide* _Rf~ 8disabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci+$G%Lusb* 8okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci+$G%Lusb* 8okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci+&G'Lusb* 8okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+&G'Lusb* 8okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&ref_clksuspend_clkbus_clkutmipipe?hostG( Lusb3-phy Vutmi_wide_4f8okayiommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-sync, 8disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-sync, 8disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXmsyscon@fd58c000rockchip,rk3588-sys-grfsysconXhsyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ isyscon@fd5a6000rockchip,rk3588-vo0-grfsysconZ` +syscon@fd5a8000rockchip,rk3588-vo1-grfsysconZ@+jsyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[+syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy+phyclk usb480m_phy0_m9phyapb 8disabledotg-portE 8disabled"syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy+phyclk usb480m_phy2_o9phyapb8okay$host-portE8okayP)%syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy+phyclk usb480m_phy3_p 9phyapb8okay&host-portE8okayP*'syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|2]q@BA.2Fq)׫ׄe/ׄ eZ р [+i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts i2cpclkh,rdefault+8okayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0dp)regulator-state-mem"regulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0dp)regulator-state-mem"serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+baudclkapb_pclk;--@txrxh.rdefaultJT 8disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclkh/rdefaulta 8disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclkh0rdefaulta 8disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + pwmpclkh1rdefaulta8okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ pwmpclkh2rdefaulta 8disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfdkpower-controller!rockchip,rk3588-power-controllerl+8okay power-domain@8l+power-domain@9  +!#" 345l+power-domain@10 +!#"6lpower-domain@11 +!#"7lpower-domain@12 +89:;lpower-domain@13 +lpower-domain@14(+<lpower-domain@15 +=lpower-domain@16+ >?@+lpower-domain@17 + ABClpower-domain@21+ DEFGHIJK+lpower-domain@23+CALlpower-domain@14 +<lpower-domain@15+=lpower-domain@22+Mlpower-domain@24+[Z]NO+lpower-domain@258+ZPlpower-domain@268+QQRlpower-domain@270+STUV+lpower-domain@28 +WXlpower-domain@29(+YZlpower-domain@30+z{[lpower-domain@31@+W\]^_lpower-domain@33!+WZ[lpower-domain@34"+WZ[lpower-domain@37%+2`lpower-domain@38&+45lpower-domain@40(alvideo-codec@fdb50000+rockchip,rk3588-vpu121rockchip,rk3568-vpuwvdpu+ aclkhclkb* iommu@fdb50800,rockchip,rk3588-iommurockchip,rk3568-iommu@v aclkiface+* ,brga@fdb80000(rockchip,rk3588-rgarockchip,rk3288-rgat+aclkhclksclk_rqp 9coreaxiahb* video-codec@fdba0000rockchip,rk3588-vepu121z+ aclkhclkc* iommu@fdba0800,rockchip,rk3588-iommurockchip,rk3568-iommu@y+ aclkiface* ,cvideo-codec@fdba4000rockchip,rk3588-vepu121@|+ aclkhclkd* iommu@fdba4800,rockchip,rk3588-iommurockchip,rk3568-iommuH@{+ aclkiface* ,dvideo-codec@fdba8000rockchip,rk3588-vepu121~+ aclkhclke* iommu@fdba8800,rockchip,rk3588-iommurockchip,rk3568-iommu@}+ aclkiface* ,evideo-codec@fdbac000rockchip,rk3588-vepu121+ aclkhclkf* iommu@fdbac800,rockchip,rk3588-iommurockchip,rk3568-iommu@+ aclkiface* ,fvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpu2ACBׄׄ+AC aclkhclk*  _vop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8+]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vopg* [hijk 8disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ aclkiface,*  8disabledgi2s@fddc0000rockchip,rk3588-i2s-tdm+mclk_txmclk_rxhclk2;l@tx* _9tx-m 8disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445mclk_txmclk_rxhclk21;l@tx* _9tx-m 8disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,mclk_txmclk_rxhclk2-;l@rx* _9rx-m 8disabledqos@fdf35000rockchip,rk3588-qossysconP 8qos@fdf35200rockchip,rk3588-qossysconR 9qos@fdf35400rockchip,rk3588-qossysconT :qos@fdf35600rockchip,rk3588-qossysconV ;qos@fdf36000rockchip,rk3588-qossyscon` [qos@fdf39000rockchip,rk3588-qossyscon `qos@fdf3d800rockchip,rk3588-qossyscon aqos@fdf3e000rockchip,rk3588-qossyscon ]qos@fdf3e200rockchip,rk3588-qossyscon \qos@fdf3e400rockchip,rk3588-qossyscon ^qos@fdf3e600rockchip,rk3588-qossyscon _qos@fdf40000rockchip,rk3588-qossyscon Yqos@fdf40200rockchip,rk3588-qossyscon Zqos@fdf40400rockchip,rk3588-qossyscon Sqos@fdf40500rockchip,rk3588-qossyscon Tqos@fdf40600rockchip,rk3588-qossyscon Uqos@fdf40800rockchip,rk3588-qossyscon Vqos@fdf41000rockchip,rk3588-qossyscon Wqos@fdf41100rockchip,rk3588-qossyscon Xqos@fdf60000rockchip,rk3588-qossyscon >qos@fdf60200rockchip,rk3588-qossyscon ?qos@fdf60400rockchip,rk3588-qossyscon @qos@fdf61000rockchip,rk3588-qossyscon Aqos@fdf61200rockchip,rk3588-qossyscon Bqos@fdf61400rockchip,rk3588-qossyscon Cqos@fdf62000rockchip,rk3588-qossyscon <qos@fdf63000rockchip,rk3588-qossyscon0 =qos@fdf64000rockchip,rk3588-qossyscon@ Lqos@fdf66000rockchip,rk3588-qossyscon` Dqos@fdf66200rockchip,rk3588-qossysconb Eqos@fdf66400rockchip,rk3588-qossyscond Fqos@fdf66600rockchip,rk3588-qossysconf Gqos@fdf66800rockchip,rk3588-qossysconh Hqos@fdf66a00rockchip,rk3588-qossysconj Iqos@fdf66c00rockchip,rk3588-qossysconl Jqos@fdf66e00rockchip,rk3588-qossysconn Kqos@fdf67000rockchip,rk3588-qossysconp Mqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 6qos@fdf71000rockchip,rk3588-qossyscon 7qos@fdf72000rockchip,rk3588-qossyscon 3qos@fdf72200rockchip,rk3588-qossyscon" 4qos@fdf72400rockchip,rk3588-qossyscon$ 5qos@fdf80000rockchip,rk3588-qossyscon Pqos@fdf81000rockchip,rk3588-qossyscon Qqos@fdf81200rockchip,rk3588-qossyscon Rqos@fdf82000rockchip,rk3588-qossyscon Nqos@fdf82200rockchip,rk3588-qossyscon" Odfi@fe060000rockchip,rk3588-dfi@&0:mpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0+CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `nnnn+<K0o0SG( Lpcie-phy* "T @ @0 @@dbiapbconfig_). 9pwrpipe+ 8disabledlegacy-interrupt-controller] npcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0+DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `pppp+<K@o@SGq Lpcie-phy* "T @ @0 A@dbiapbconfig_*/ 9pwrpipe+ 8disabledlegacy-interrupt-controller] pethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref* !_$ 9stmmaceth[hr+rst 8disabledmdiosnps,dwmac-mdio+stmmac-axi-configrrx-queues-configsqueue0queue1tx-queues-configtqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(+b_eTosatapmaliverxoobrefasic)+8okaysata-port@0;@Gq Lsata-phyH W sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVqsatapmaliverxoobrefasic)+ 8disabledsata-port@0;@G( Lsata-phyH W spi@fe2b0000 rockchip,sfc+@+/0clk_sfchclk_sfc+ 8disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  biuciuciu-driveciu-samplefq rdefaulthuvwx* (8okayyzmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +biuciuciu-driveciu-samplefq rdefaulth{* % 8disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.2-., B n6 (+,*+-.corebusaxiblocktimerq h|}~rdefault(_9corebusaxiblocktimer8okayi2s@fe470000rockchip,rk3588-i2s-tdmG++/(mclk_txmclk_rxhclk2)-;--@txrx* &_*+ 9tx-mrx-m*rdefault(h 8disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}umclk_txmclk_rxhclk;--@txrx_^_ 9tx-mrx-m*rdefault(h 8disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+i2s_clki2s_hclk2;@txrx* &rdefaulth 8disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%i2s_clki2s_hclk2";@txrx* &rdefaulth 8disabledinterrupt-controller@fe600000 arm,gic-v3 `h ]EaO8Z+msi-controller@fe640000arm,gic-v3-itsdZiomsi-controller@fe660000arm,gic-v3-itsfZippi-partitionsinterrupt-partition-0tinterrupt-partition-1t dma-controller@fea10000arm,pl330arm,primecell@ VW}+n apb_pclk-dma-controller@fea30000arm,pl330arm,primecell@ XY}+o apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ i2cpclk>hrdefault+ 8disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| i2cpclk?hrdefault+ 8disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} i2cpclk@hrdefault+ 8disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ i2cpclkAhrdefault+ 8disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkBhrdefault+ 8disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+spiclkapb_pclk;--@txrx hrdefault+ 8disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+spiclkapb_pclk;--@txrx hrdefault+ 8disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+spiclkapb_pclk;@txrxhrdefault+8okay2B pmic@0rockchip,rk806B@ rdefaulth)))) ) ) ) $) 0) <) I V) c p })  dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 vdd_gpu_s0dp~0 regulator-state-mem"dcdc-reg2vdd_cpu_lit_s0dp~0regulator-state-mem"dcdc-reg3 vdd_log_s0 L q0regulator-state-mem" qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-mem"dcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem" Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg7vdd_2v0_pldo_s30regulator-state-mem  dcdc-reg8 vcc_3v3_s32Z2Zyregulator-state-mem  2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem"dcdc-reg10 vcc_1v8_s3w@w@regulator-state-mem  w@pldo-reg1 avcc_1v8_s0w@w@regulator-state-mem"pldo-reg2 vcc_1v8_s0w@w@regulator-state-mem" w@pldo-reg3 avdd_1v2_s0OOregulator-state-mem"pldo-reg4 vcc_3v3_s02Z2Z0regulator-state-mem"pldo-reg5 vccio_sd_s0w@2Z0zregulator-state-mem"pldo-reg6 pldo6_s3w@w@regulator-state-mem  w@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem  qnldo-reg2vdd_ddr_pll_s0 P Pregulator-state-mem" Pnldo-reg3 avdd_0v75_s0 q qregulator-state-mem"nldo-reg4 vdd_0v85_s0 P Pregulator-state-mem"nldo-reg5 vdd_0v75_s0 q qregulator-state-mem"spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+spiclkapb_pclk;@txrx hrdefault+ 8disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+baudclkapb_pclk;-- @txrxhrdefaultTJ 8disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+baudclkapb_pclk;- - @txrxhrdefaultTJ8okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+baudclkapb_pclk;- - @txrxhrdefaultTJ 8disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+baudclkapb_pclk; @txrxhrdefaultTJ 8disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+baudclkapb_pclk; @txrxhrdefaultTJ 8disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+baudclkapb_pclk; @txrxhrdefaultTJ8okayserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+baudclkapb_pclk;ll@txrxhrdefaultTJ8okayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+baudclkapb_pclk;l l @txrxhrdefaultTJ 8disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+baudclkapb_pclk;l l @txrxhrdefaultTJ 8disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkhrdefaulta 8disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkhrdefaulta 8disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK pwmpclkhrdefaulta 8disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK pwmpclkhrdefaulta 8disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkhrdefaulta 8disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkhrdefaulta 8disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON pwmpclkhrdefaulta 8disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON pwmpclkhrdefaulta 8disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkhrdefaulta 8disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkhrdefaulta 8disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ pwmpclkhrdefaulta 8disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ pwmpclkhrdefaulta 8disabledthermal-zonespackage-thermal   'tripspackage-crit 78 C criticalbigcore0-thermal d  'tripsbigcore0-alert 7L Cpassivebigcore0-crit 78 C criticalcooling-mapsmap0 N Sbigcore2-thermal d  'tripsbigcore2-alert 7L Cpassivebigcore2-crit 78 C criticalcooling-mapsmap0 N S littlecore-thermal d  'tripslittlecore-alert 7L Cpassivelittlecore-crit 78 C criticalcooling-mapsmap0 N0 Scenter-thermal   'tripscenter-crit 78 C criticalgpu-thermal d  'tripsgpu-alert 7L Cpassivegpu-crit 78 C criticalcooling-mapsmap0 N Snpu-thermal   'tripsnpu-crit 78 C criticaltsadc@fec00000rockchip,rk3588-tsadc+tsadcapb_pclk2B_VW9tsadc-apbtsadc b y h rdefaultsleep 8okayadc@fec10000rockchip,rk3588-saradc +saradcapb_pclk_U 9saradc-apb 8disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkChrdefault+8okayrtc@51haoyu,hym8563Q hym8563rdefaulth i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkDhrdefault+ 8disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkEhrdefault+ 8disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+spiclkapb_pclk;l l@txrx hrdefault+ 8disabledefuse@fecc0000rockchip,rk3588-otp +otpapb_pclkphyarb_ 9otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[}+p apb_pclklphy@fed60000rockchip,rk3588-hdptx-phy +TrefapbE8_#cde!""9phyapbinitcmnlaneroplllcpll[ 8disabledphy@fed80000rockchip,rk3588-usbdp-phyE+lVrefclkimmortalpclkutmi(_   9initcmnlanepcs_apbpma_apb    * 8disabled#phy@fee00000rockchip,rk3588-naneng-combphy+vW refapbpipe2BE_<C9phyapb :+ L8okayqphy@fee20000rockchip,rk3588-naneng-combphy+xW refapbpipe2BE_>E9phyapb :+ L8okay(sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl[+gpio@fd8a0000rockchip,gpio-bank+qr  b ] gpio@fec20000rockchip,gpio-bank+st  b ] gpio@fec30000rockchip,gpio-bank+uv  b@ ] gpio@fec40000rockchip,gpio-bank+wx  b` ] gpio@fec50000rockchip,gpio-bank+yz  b ] pcfg-pull-up npcfg-pull-down {pcfg-pull-none pcfg-pull-none-drv-level-2  pcfg-pull-up-drv-level-1 n pcfg-pull-up-drv-level-2 n pcfg-pull-none-smt  auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout |emmc-bus8 }emmc-clk ~emmc-cmd emmc-data-strobe eth1fspigmac1gpuhdmii2c0i2c0m2-xfer ,i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m0-xfer   i2c7i2c7m0-xfer   i2c8i2c8m0-xfer   i2s0i2s0-lrck i2s0-sclk i2s0-sdi0 i2s0-sdi1 i2s0-sdi2 i2s0-sdi3 i2s0-sdo0 i2s0-sdo1 i2s0-sdo2 i2s0-sdo3 i2s1i2s1m0-lrck i2s1m0-sclk i2s1m0-sdi0 i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins /pwm1pwm1m0-pins 0pwm2pwm2m1-pins  1pwm3pwm3m0-pins 2pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` {sdmmcsdmmc-bus4@ xsdmmc-clk usdmmc-cmd vsdmmc-det wspdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut-org uart0uart0m1-xfer  .uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m0-xfer   uart7uart7m2-xfer   uart8uart8m1-xfer   uart9uart9m1-xfer   vopbt656gpio-functsadc-gpio-func eth0gmac0ledsled_user_en pcie2pcie2-0-rst pcie3pcie3x2-rst pcie3x2-vcc3v3-en pcie3x4-rst pcie3x4-vcc3v3-en hym8563hym8563-int usbvcc5v0-host-en usb@fc400000rockchip,rk3588-dwc3snps,dwc3@@+ref_clksuspend_clkbus_clk?otg GLusb2-phyusb3-phy Vutmi_wide* _Sf 8disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+usb2phy@4000rockchip,rk3588-usb2phy@+phyclk usb480m_phy1_n9phyapb 8disabledotg-portE 8disabledi2s@fddc8000rockchip,rk3588-i2s-tdm܀+mclk_txmclk_rxhclk2;l@tx* _9tx-m 8disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@+99?mclk_txmclk_rxhclk26;l@tx* _9tx-m 8disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀+++'mclk_txmclk_rxhclk2(;l@rx* _9rx-m 8disabledi2s@fde00000rockchip,rk3588-i2s-tdm+&&"mclk_txmclk_rxhclk2#;l@rx* _9rx-m 8disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `+<KSG Lpcie-phy* "T @ @0 @@dbiapbconfig_&+ 9pwrpipe8okayrdefaulth  legacy-interrupt-controller] pcie-ep@fe150000rockchip,rk3588-pcie-epP @ @ @ @0dbidbi2apbaddr_spaceatu0+@E;JOt)aclk_mstaclk_slvaclk_dbipclkauxpipe +syspmcmsglegacyerrdma0dma1dma2dma3<SG Lpcie-phy* "_&+ 9pwrpipe 8disabledpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0+AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `+<KSG Lpcie-phy* "T @ @@0 @@@dbiapbconfig_', 9pwrpipe8okayrdefaulth  legacy-interrupt-controller] pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0+BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr `+<K o SG Lpcie-phy* "T @ @0 @@dbiapbconfig_(- 9pwrpipe+8okayrdefaulth  legacy-interrupt-controller] ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref* !_# 9stmmaceth[hr+ 8disabledmdiosnps,dwmac-mdio+stmmac-axi-configrx-queues-configqueue0queue1tx-queues-configqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(+c`fUpsatapmaliverxoobrefasic)+ 8disabledsata-port@0;@G Lsata-phyH W phy@fed90000rockchip,rk3588-usbdp-phyE+mWrefclkimmortalpclkutmi(_9initcmnlanepcs_apbpma_apb    * 8disabledphy@fee10000rockchip,rk3588-naneng-combphy+wW refapbpipe2BE_=D9phyapb :+ L8okayphy@fee80000rockchip,rk3588-pcie3-phyE+ypclk_H9phy :+ 8okayopp-table-cluster0operating-points-v2  opp-1008000000 <  L L~ @opp-1200000000 G  4 4~ @opp-1416000000 Tfr  ~ @ 'opp-1608000000 _"  P P~ @opp-1800000000 kI ~~~ @opp-table-cluster1operating-points-v2 opp-1200000000 G  L LB@ @opp-1416000000 Tfr   B@ @opp-1608000000 _"  B@ @opp-1800000000 kI  P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000   B@B@B@ @opp-table-cluster2operating-points-v2 opp-1200000000 G  L LB@ @opp-1416000000 Tfr   B@ @opp-1608000000 _"  B@ @opp-1800000000 kI  P PB@ @opp-2016000000 x) HHB@ @opp-2208000000 h llB@ @opp-2400000000   B@B@B@ @opp-tableoperating-points-v2!opp-300000000   L L Popp-400000000 ׄ  L L Popp-500000000 e  L L Popp-600000000 #F  L L Popp-700000000 )'  ` ` Popp-800000000 /  q q Popp-900000000 5  5 5 Popp-1000000000 ;  P P Pgpio-leds gpio-ledsled-0 3 heartbeat  9heartbeatrdefaulthvcc12v-dcin-regulatorregulator-fixed vcc12v_dcinvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@)vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3)chosen Oserial2:1500000n8vcc3v3-pcie2x1l0-regulatorregulator-fixedvcc3v3_pcie2x1l02Z2Z [yvcc3v3-pcie3x2-regulatorregulator-fixed l rdefaulthvcc3v3_pcie3x22Z2Z [)vcc3v3-pcie3x4-regulatorregulator-fixed l rdefaulthvcc3v3_pcie3x42Z2Z [)vcc5v0-host-regulatorregulator-fixed l rdefaulth vcc5v0_hostLK@LK@)* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesno-mapclock-namespower-domainsstatusdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosiommusreg-namesrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellswakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyrockchip,phy-grfopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendcolorlinux,default-triggerstdout-pathstartup-delay-usenable-active-highgpio